Comparison of Substrate Materials for High Concentration CPV Submounts

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Comparison Of Substrate Materials For High Concentration CPV  Submounts

Multijunction photovoltaics on germanium substrates are wired in series in order to boost voltage. Each diode is typically mounted on a dielectric substrate, which is then mounted on a heatsink. The purpose of this study is to calculate the relationship between substrate thermal conductivity, solar flux and chip temperature assuming an unlimited heatsink.

Thermal finite element analysis was used to model the steady state, maximum surface temperature of a standard 1 x 1 cm2 multi-junction die as a function of: number of suns, dielectric material (direct bond copper on Al2O3 versus metallized BeO) and cold plate temperature. Minimizing the thermal resistance of the stack becomes critical at high solar flux. For a typical assembly stack, the chip temperature on BeO is cooler than the chip temperature on conventional DBCu alumina by 3.0 °C at 500 suns and 10.6 °C at 1500 suns.

Photovoltaics Categorization

Photovoltaics can be generally divided into three categories: crystalline silicon, thin film, and concentrator photovoltaics (CPV). Researchers are striving to minimize the money spent/ watt of each technology. Of the three PV technologies, CPV perhaps offers the greatest potential for long term cost reduction due to continual increases in multijunction chip efficiency [1] and improved optics.

One approach to reduce the money spent /watt of CPV has been to increase the number of suns focused onto the CPV chip. Research has been published on concentrations of 2000 suns and greater [2]. Assuming an optimal chip efficiency of 40%, 2000 suns would still require 120 W/cm2 of heat to be dissipated from the chip. By way of comparison, the space shuttle experiences 10 W/cm2 during re-entry, and the throat of a rocket nozzle generates 100 W/cm2 [3].

This study examines the role the substrate material plays in the CPV submount. Since multijunction dice are wired in series, the ideal substrate should be a dielectric that also is a good conductor of heat. Here, we consider two substrate materials: conventional direct bond copper alumina (DBCu alumina) and BeO. We calculate the dependence of maximum chip temperature as a function of substrate material, number of suns and other parameters.

Materials in the model

For all simulations, three materials were fixed: the multijunction chip, the die attach material and the gap filler material. We assume the multijunction chip is comprised of III-V epi layers on a bulk germanium substrate. It is attached to the substrate by a commercially available silver-filled epoxy with a thermal conductivity of 29 W/m-K [4]. The ceramic substrate is bonded to a heatsink using a commercially available gap filler material with a thermal conductivity of 5 W/m-K [5].

Two different ceramic substrates were compared: BeO and DBCu alumina. DBCu alumina is available in a wide range of copper and alumina thickness combinations. For this study, we assume a conventional 15/25/15 DBCu alumina. The layer stack-up on the DBCu substrate is presented in Table 1.

Table 1: Layer Stack on DBCu

In DBCu, the copper and alumina layers are bonded by an aluminum-copper-oxide phase. The bonding of the copper to the alumina constrains the surface thermal expansion of the copper to be closer to the CTE of germanium. CPV presents a very demanding temperature cycling challenge for substrate materials.

The CPV submount must withstand a sudden swing from a chip surface temperature of 100°C – 120°C when the sun is out, to the ambient air temperature (if in a cold winter climate, -20°C) when a cloud passes overhead. Such thermal cycles will occur numerous times over the rated lifetime of the CPV installation (20 – 30 years). The integrity of the aluminum-copper-oxide bond phase between the copper and alumina layers must withstand these repeated thermal cycles without failure since delamination would catastrophically increase the thermal resistance of the DBCu.

The BeO is assumed to be 99.5% BeO, Thermox 995. It is assumed to be metallized on one face with a 15 µm thick film Mo/Mn metallization, plated with Ni and a flash of gold. The backside of the BeO is not metallized. The layer stack-up with BeO is shown in Table 2. Although not modeled in this study, bulk BeO has a good CTE match to Ge, so multijunction chips on BeO should resistant to thermal stresses upon temperature cycling. There are no restrictions to using BeO in a solar application, apart from labeling regulations. BeO is not, and has never been, on the list of materials prohibited by ROHS. BeO can be returned to its supplier and recycled.

Table 2: Layer Stack on BeO

 

Input Assumptions

The multijunction chip is assumed to be the Spectrolab CDO-100, which has an aperture area of 0.99 cm x 1.0 cm [6]. Plotted data for efficiency at maximum power at various solar fluxes was fitted to an equation using a quadratic fit. The empirical data published by Spectrolab extended from 10 to 1000 suns. To estimate efficiency performance from 1000 to 2000 suns, the curvefit equations were extrapolated using a French curve extrapolation. However, the reader is cautioned that all calculations on CDO-100 chip performance above 1000 suns is based upon extrapolations of the Spectrolab’s empirical measurements.

The incident thermal flux of 1 sun is assumed to be 0.1 W/cm2 and assumed to be uniform over the area of the chip aperture. We assume that 100% of the heat generated in the chip is conducted to the backside of the die, we ignore convective and radiative losses from the top and sides of the chip. The thermal heat dissipated through the thickness of Ge is simply calculated as follows:

H = 0.1N(1 – ?) (1) where H is the heat flux emanating from the backside of the Ge die in W/cm2, N is the number of suns, and ? is the photovoltaic efficiency. Since ? is a function of temperature, the finite element analysis model iteratively calculated efficiency and chip temperature following the empirical relationship reported by Spectrolab, (which was extrapolated for concentrations exceeding 1000 suns.)

For simplicity, the heatsink was assumed to be ‘infinite’ namely, able to sink away any of the thermal flux transmitted by the backside gap filler material. Also, the temperature of the heatsink was assumed to be equal to the ambient air temperature. Although outside the scope of this study, the cost, size and complexity of the heatsink increases dramatically when conducted thermal fluxes exceed about 40 W/cm2. CPV systems where the concentration exceeds 800 suns will probably require pumped water-cooled heatsinks connected to a radiator.

Finite element analysis

Finite element analysis was performed using COSMOS/M Geostar 2007 software. One quarter of the chip was modeled to take advantage of the four-fold symmetry of the package. An initial efficiency of the multijunction chip was assumed. This was used to calculate the input heat flux that was applied to the surface representing the top of the die.

The bottom surface of the model represents the interface between the gap filler and the heat sink. The interface was assumed to be at the temperature of the infinite heat sink, and this temperature was prescribed at all nodes on this surface. The efficiency of the multijunction chip was calculated at the output temperature of the model. This was then used to calculate the heat flux to be used in the next iteration of the model. This process was repeated until the values of the input and output efficiencies fell within 0.1% agreement.

It would seem that a more exact model could be obtained by including the heat sink and the convective heat transfer out of it. However, the convective heat transfer coefficient would first have to be experimentally determined as a function of temperature for a given heat sink configuration. With this experimental data in hand, the model would then have to be iterated to determine both the input heat flux on the die and the output heat flux from the heat sink based on the local temperatures. There is a possibility that these iterations may not converge to a unique solution. For the sake of simplicity in this model, it was determined to assume an infinite, constant temperature heat sink.

Figure 1: Schematic of the Submount on DBCu Alumina.

 

Schematic diagrams of the two submount assemblies are shown in Figures 1 and 2.

Figure 2: Schematic of the Submount on BeO.

Study Results

Simulations were run with three different heatsink temperatures: 25°C, 38°C and 50°C. The results are summarized in the graphs of Figures 3 – 5.

3(a)

 

3(b)

 

Figure 3: Heatsink (ambient) temperature fixed at 25°C. (a) Photovoltaic efficiency as a function of solar concentration and (b) Maximum photovoltaic temperature as a function of solar concentration.

4(a)

 

4(b)

 

Figure 4: Heatsink (ambient) temperature fixed at 38°C. (a) Photovoltaic efficiency as a function of solar concentration and (b) Maximum photovoltaic temperature as a function of solar concentration.

 

5(a)

 

5(b)

 

Figure 5: Heatsink (ambient) temperature fixed at 50°C. (a) Photovoltaic efficiency as a function of solar concentration and (b) Maximum photovoltaic temperature as a function of solar concentration.

Discussion & Conclusion

Figures 3 – 5 can be used to draw some useful comparisons between BeO and the particular DBCu alumina modeled. When the heatsink is held at 38°C or 50°C, the BeO substrate keeps the chip cooler than DBCu 3 C° at 500 suns and 10 - 11 C° at 1500 suns.

Since the maximum recommended temperature of the photodiode is about 120°C, this upper temperature limit can be used to look up the maximum number of suns that a particular scenario can tolerate. Not surprisingly, the cooler the heatsink the cooler the temperature of the photovoltaic chip. In the case of the BeO substrate: a heatsink temperature held at 25°C enables a limit of 2200 suns while a heatsink temperature held at 50°C enables a limit of 1600 suns.

A summary of the number of suns that will result in chip temperature of 120°C is shown in Table 3.

Table 3: Maximum number of Suns that can be tolerated

 

Comparison Of Substrate Materials For High Concentration CPV Submounts References

[1] “NREL Solar Cell Sets World Efficiency Record at 40.8 Percent,” NREL News Release NR-2708, Aug.13, 2008.

[2] “IBM Research Unveils Breakthrough In Solar Farm Technology” IBM press release, May 15, 2008.

[3] P. Chinoy, “Thermal Interface Materials (TIMs) for IC Cooling,” presented at IMAPS New England meeting, October 22, 2008.

[4] For example, see datasheet for Epo-Tek H20E silver filled epoxy; www.epotek.com

[5] For example, see datasheet for Berquist Gap Pad 5000S35; www.bergquistcompany.com

[6] Boeing Spectrolab, datasheet CDO-100 Concentrator Photovoltaic Cell, updated: 2007-11-21; www.spectrolab.com